If you do not find a position that fits your unique abilities, feel free to email us at: hr@photonic-tech.com

  • Analog Design Manager (Shanghai, Shenzhen)
  • Analog Design Engineer (Shanghai, Shenzhen)
  • CLOSED: Analog Layout Engineer (Shanghai, Shenzhen)
  • Digital Verification Engineer (Shanghai, Shenzhen)
  • Digital Design Engineer (Shanghai, Shenzhen)
  • Physical Design Engineer (Shanghai, Shenzhen)
  • Android Software Engineer (Shanghai)
  • Signal Integrity Engineer (Shanghai)
  • Test / System Validation Engineer (Shanghai, Shenzhen, Wuhan)
  • Field Application Engineer (Shanghai, Shenzhen, Wuhan)
  • ATE Engineer (Shanghai)
  • Marketing Engineer (Shanghai, Shenzhen, Silicon Valley)
  • Sales Manager (Shanghai, Shenzhen, Silicon Valley)
  • Product Management Engineer / Manager (Shanghai, Silicon Valley)
  • Senior Product Engineer (Shanghai)
  • CLOSED: Production Planner (Shanghai)
  • CLOSED: Recruiter (Shanghai, Shenzhen)
  • Executive Assistant (Shanghai)

Analog Design Manager

模拟设计经理

Shanghai China, Shenzhen China

Responsibilities:

  • You will lead your team to design, analyze, and implement high-performance (>10GHz) PLL, wireline amplifiers, CDR, SERDES, PLL, PAM4, TDCs, TOF, low-noise amplifiers, transmitters, power-amplifiers and power-drivers, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc.
  • Use EDA tools (Cadence, Mentor) to run simulation and function verification.
  • Guide layout engineer to optimize layout.
  • Chip debug and testing individually and with the team.
  • Other tasks assigned by line manager.

Qualifications:

  • MSEE in analog IC design with around 5 years’ experience.
  • Hands-on design experience with multi-gigahertz SERDES transmitter/receiver, TIA, PLL, CDR, LNA, ToF, Temperature Sensor, power management IC or low-speed ADC/amplifier.
  • Great team management skills.
  • Experience in Cadence EDA tools.
  • Team player with good communication skills.

Analog Design Engineer

模拟电路设计工程师

Shanghai China, Shenzhen China

Responsibilities:

  • You will design, analyze, and implement high-performance (>10GHz) PLL, wireline amplifiers, CDR, SERDES, PLL, PAM4, TDCs, TOF, low-noise amplifiers, transmitters, power-amplifiers and power-drivers, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc.
  • Use EDA tools (Cadence, Mentor) to run simulation and function verification.
  • Guide layout engineer to optimize layout.
  • Chip debug and testing individually and with the team.
  • Other tasks assigned by line manager.

Qualifications:

  • MSEE in analog IC design.
  • Hands-on design experience with multi-gigahertz SERDES transmitter/receiver, TIA, PLL, CDR, LNA, ToF, Temperature Sensor, power management IC or low-speed ADC/amplifier.
  • Great team management skills.
  • Experience in Cadence EDA tools.
  • Team player with good communication skills.

Analog Layout Engineer

模拟版图工程师

Shanghai China, Shenzhen China

Responsibilities:

  • You will optimize the layout and high-frequency (multi-gigahertz) routing of high-precision analog circuits, such as:
    high-speed amplifiers, wireline SERDES, PLL, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc.
  • Use EDA tools (Cadence, Mentor, Allegro) to layout, extract, and verify the high-performance layout.
  • Work and iterate with analog/RF engineers to optimize the layout performance.

Qualifications:

  • BSEE in analog IC design with minimal 3 years’ experience.
  • Experience in Cadence EDA tools.
  • Team player with good communication skills.
  • Desired: Experience with the layout of SERDES transmitter/receiver, PLL, TIA, CDR, LNA etc.
  • Desired: Experience with the layout of SERDES transmitter/receiver, PLL, TIA, CDR, LNA etc.

Digital Verification Engineer

高级数字电路验证工程师

Shanghai China, Shenzhen China

Responsibilities:

  • This position is for a digital-ASIC verification engineer to build next-generation analog/mixed-signal SoC chipsets.
  • Responsible for all aspects of UVM (Universal Verification Methodology), from start to finish. Good knowledge of communication protocols and associated verification IPs (VIPs). Extensive experience with assertions, cover properties, constrained random testing.
  • Work with other digital designers to verify many aspects of ASIC design flow including: architecture, RTL coding/Verification, Synthesis, DFT, STA and P&R (for backend designer).
  • Participate in chip debug, validation, and marketing specifications.

Qualifications:

  • MSEE, Junior:2-3 years’ verification experience, Senior: 5-6 years’ experience.
  • REQUIRED: Experience in metrics-driven verification methodology (System-Verilog/UVM based).
  • Excellent knowledge of ASIC design, such as arithmetic structure (addition, multiplication, integration), timing analysis, DFT, meta-stability, etc.
  • Fundamental understanding of digital signal processing, such as FIR/IIR filter structure, error correction, and decimation.
  • Desired usage experience of mainstream industry-standard EDA tools, such as VCS/NC, Design Compiler, PrimeTime, Formality/ Conformal and Tetramax/DFT compiler.
  • Experience in other vertical aspects of ASIC design (front-end and back-end) will be a great plus.
  • Experience in perl/python/tcl scripts is a plus.

Digital Design Engineer

数字电路设计工程师

Shanghai China, Shenzhen China

Responsibilities:

  • This position is for a digital/ASIC design engineer to build next-generation analog/mixed-signal SoC chipsets.
  • Work closely with analog/mixed-signal designers to build robust system-on-chip that is reliable under PVT variation.
  • Handle many aspects of ASIC design flow including: architecture, RTL coding/Verification, Synthesis, DFT, STA and P&R (for backend designer).
  • Participate in chip debug, validation, and marketing specifications.

Qualifications:

  • MSEE in digital IC design.
  • Excellent knowledge of ASIC design, such as arithmetic structure (addition, multiplication, integration), timing analysis, DFT, meta-stability, etc.
  • Fundamental understanding of digital signal processing, such as FIR/IIR filter structure, error correction, and decimation.
  • Desired usage experience of mainsteam industry-standard EDA tools, such as VCS/NC, Design Compiler, PrimeTime, Formality/ Conformal and Tetramax/DFT compiler.
  • Experience in several vertical aspects of ASIC design (front-end and back-end) will be a great plus.
  • Experience in common protocols, such as bus design (I2C, AHB/APB/AXI), datapath design (Filter, correlation or Cordic) and logic control (PCS or MAS) is a plus.
  • Experience in metrics-driven verification methodology (System-Verilog/UVM based) is a plus.
  • Experience in mixed-signal SOC design is a plus.
  • Experience in perl/python/tcl scripts is a plus.

Physical Design Engineer

数字后端设计工程师

Shanghai China, Shenzhen China

Responsibilities:

  • Perform backend design including floor planning, place and routing, timing optimization, and final DRC/LVS.
  • Perform Low Power design/power analysis/formal verification/STA-ECO flow.
  • Solve deep sub-micron design problems such as leakage, power, signal integrity, timing closure, DRC/DFM etc.
  • Develop Perl/TCL/Shell scripts to enhance IC physical design flow and methodology.
  • Other tasks assigned by line manager.

Qualifications:

  • BSEE, MSEE or higher.
  • 2-year experience of large ASIC backend designs.
  • Experience with Synopsys and/or Cadence design tools.
  • Familiar with 45/40nm or lower CMOS process designs.
  • Having successful tape out experience will be a great plus.
  • Good communication skills, team spirit and be anxious to learn during daily work.

Android Software Engineer

安卓驱动开发工程师

Shanghai China

Responsibilities:

  • Develop device driver for Android AP/Windows.
  • Implement API Guide related document.
  • Work with teams to build up test bench for devices.
  • Other tasks assigned by line manager.

Qualifications:

  • 3-year experience in Software development.
  • Knowledge on android system.
  • Knowledge on windows device driver.
  • Knowledge on Linux kernel.
  • Good at C, C++, JAVA.
  • Knowledge on I2C/SPI protocol is a plus.
  • Team work, self-driven, problem solving.

Signal Integrity Engineer

信号完整性工程师

Shanghai China

Responsibilities:

  • In this position, you will work with the IC design team that develops high-speed laser drivers and CDRs used within 5G and Data cernter optical modules.
  • Use EDA tools (Cadence, Mentor) to run simulation and function verificationYou will be responsible for high-speed serial interface signal integrity and power integrity covering from package to evaluation board development.

Qualifications:

  • Strong fundamentals on Microwave and transmission line theory.
  • Experience working with the actual product package/board design and analysis, SI/PI methodology development, lab validations.
  • Be familiar with signal and power integrity issues of high speed serial interfaces.
  • Be familiar with 2D/3D simulation tools such as ADS, HFSS, Sigrity, etc.
  • Be familiar with lab equipment, such as: VNA, TDR, oscilloscope, spectrum analyzer, etc.
  • Matlab/Python programming skill is a plus.
  • Good communication skills.

Test/ System Validation Engineer

芯片硬件测试工程师

Shanghai China, Shenzhen China, Wuhan China

Responsibilities:

  • Evaluate and test several of our state-of-the-art high-speed SOC products. These include high-frequency multi-gigahertz analog/mixed-signal chips, with significant performance issues, such as: channel cross talk, input-referred noise, phase noise, output bandwidth, power-supply noise, impedance matching.
  • Occasionally (<10%) travel to test lab and customer locations, testing our chips in their labs.
  • Other tasks assigned by line manager.

Qualifications:

  • Bachelor’s degree with minimum 1-year experience as FAE, IC designer, or test engineer.
  •  Experience and understanding of impedance matching, noise processes, phase noise, multi-GHz performance.
  • Occasionally (20%) be willing to travel to test lab and customer locations, testing our chips in their labs.
  • Can read system datasheets, understand, and debug interactions between different blocks.
  • Desired: previous experience with basic IC design, PCB prototyping, IC testing.
  • Desired: High-level system programming, such as C/C++, python/Perl, LabView, Matlab.
  • Desired: Lab experience using oscilloscopes, signal/pattern generators, BERT, spectrum analyzer, AWG, BERT.
  • Preferred: Experience with high-speed optical testing, including BERT, eye mask, jitter, optical coupling, etc.
  • Preferred: Experience with interfacing with ATE and wafer-level testing/sorting.

Field Application Engineer

现场应用工程师

Shanghai China, Shenzhen China, Wuhan China

Responsibilities:

  • Support domestic and international optical communication customers in product design, design validation, silicon test and application with optical ICs such as high-speed TIA, laser driver and limiting amplifier, CDR, etc.
  • Track project from new opportunity to mass production.
  • Troubleshoot technical problem in both pre-sale and post-sale phases.
  • Communicate across marketing, design team and testing team for technical issue and new product definition.

Qualifications:

  • BSEE or MSEE, 1-year relevant working experience in application of analog ICs for optical communication, such trans-impedance amplifier, limiting amplifier, laser driver and clock-and-data recovery etc.
  • Deep knowledge in optical module, system and its application such as TOSA, ROSA, CWDM, AOC, PON, etc. Hands-on test and troubleshooting skills from silicon to product validation.
  • Ability to program with Scripting languages (i.e. Python) and high-level languages (i.e. C/C or Visual Basic, etc.).
  • Able to work with test equipment (i.e. BERT, DCA, Oscilloscope, etc.).
  • Strong analytical and communication skills for efficient customer communication.
  • Design experiences in optical front-end is a plus.
  • Travel required ~ 30%.

ATE Engineer

ATE测试工程师

Shanghai China

Responsibilities:

  • Develop and document test plan for new product.
  • Work with DFT and design teams to evaluate new product testability.
  • Design and debug test SW & HW for Production, Characterization & Reliability.
  • Work with DFT and design teams to debug new silicon.
  • Bring quality and cost effective test solution for mass production.
  • Coordinate test related activities with both internal and external group.

Qualifications:

  • Junior or senior.
  • 2 years+ relevant working experience and in depth knowledge of semiconductor testing process.
  • Solid understanding of high speed digital and analog circuits, design for test and manufacturing concepts.
  • Expertise in Semiconductor Test Methodology.
  • Team player with good communication skills.
  • Experience working with Digital, Mixed Signal, and SOC Devices with hands on ATE experience.
  • Strong Programming skills for writing and debugging test programs and HW related issues.
  • Ability to program with Scripting languages (i.e. Perl, Python) and high level languages (i.e. C/C or Visual Basic, etc.).
  • Able to work with test equipment (i.e. VNA, DCA, Oscilloscope, etc.).

Product Marketing Engineer

市场研究员

Shanghai China, Shenzhen China, Silicon Valley USA

Responsibilities:

  • Responsible for the whole process of product life cycle: from market analysis, demand analysis to product definition, implementation, release and promotion.
  • Investigate the status and development trend of consumer IC market, visit customers / distributors regularly and understand the needs / feedback, assist the company to plan product roadmap and write go-to-market strategic plan.
  • According to the results of product research and planning, define and manage product requirements, organize the specific definition of products, plan the project progress / mass production / promotion schedule, write the marketing requirement document, and facilitate the project approval.
  • Work with R&D, testing, operation and sales to determine the competitive advantage of proposed products and optimize the cost of products, and service to end-customers.
  • Participate in product project progress, cooperate with project management team, R&D, testing, operation and sales to track project status, adjust product strategy in time according to actual progress, and facilitate product delivery, release and promotion.
  • Cooperate with technical support and sales team to make promotion strategy and plan.
  • Organize regular communication and product training for technical support, sales, agents and customers.
  • Be responsible for product price management and promotion strategy.
  • Collect Competitive analysis data and participate in trade shows to keep abreast of industry trends and dynamics.
  • Other tasks assigned by line manager.

Qualifications:

  • BSEE or above.
  • 2-3 years’ marketing or FAE experience in IC design companies focusing on TWS (True Wireless Stereo), wearables and other consumer products.
  • Experience in chip definition, design, chip application and technical support is preferred.
  • Strong logical thinking abilities and sharp acumen.
  • Excellent presentation and communication skills in both Chinese and English.
  • Fast learner on new technology / new applications / new products.

Sales Manager

消费芯片销售经理

Shanghai China, Shenzhen China, Silicon Valley USA

Responsibilities:

  • Responsible for the consumer electronics sales/market, including 3D TOF chips, health/fitness chips, optical sensors. Developing and monitoring and different industries, including Cellphone, home appliance, AIOT, industrial usage, TWS/Watch.
  • Develop and keep good relationship with module makers, solution makers and end customers. Be in charge of sales process with them.
  • Be in responsible for the direct and indirect customers from worldwide customers, focus on China Mainland, Taiwan and South Korea.
  • Follow company’s sales target and strategy, develop new businesses, maintain ongoing projects, provide precise forecast to inner supply chain department. Be in charge of finding right contacts, design in, design win and mass producing.
  • Update customers’ status, market information, make work plan, every week in sales meeting, to keep focus, and direction right.
  • Drive and allocate FAE, PM and supply chain resources to provide good service to customers, to reach sales target.
  • Responsible for market information collection and industry analysis reports.

Qualifications:

  • Bachelor/Master degree with technical background.
  • 3~5 years sales or marketing experience of CCM chips, or other chips in cellphone, home appliance, AIOT, wearable.
  • Good industrial networking in related industries.
  • Ability to work under limited supervision.
  • Strong communication and negotiation skills with customers and inner departments.
  • Proven problem-solving skill.

Product Management Engineer/Manager

产品管理工程师/经理

Shanghai China, Silicon Valley USA

Responsibilities:

  • Program management: Program management for the whole product development flow from project kick-off to production release. A key team player to control project schedule and expense with strong communication skills and solid technical understanding of NPI, drive team to achieve on-time delivery and production release success, effectively predict, coordinate and follow-up, including effective communication with internal and external customers, R&D team, and technical support team, identify and analyze project risks and take timely measures to prevent and reduce losses, participate in the review and decision-making of major milestones in the product development process.
  • Product life-cycle management: manage internal and external change request to the datasheet spec of a product in development and MP, lead analysis in rationality assessment, impact scope and conduct plan of the change request, key contact to bridge customer demands and internal operation. Conduct product cost management (such as cost down roadmap), stock management, inventory management and sales management through product lifecycle.
  • Other tasks assigned by line manager could be as following as needed: product planning, product definition based on company business strategy and market analysis, product pricing strategy, customer engagement and supplier communication.

Qualifications:

  • BSEE or MSEE in ME, EE, CS, etc.
  • Minimal 5 years’ experience in one of the following domains:
    1) Program Management (from project kick-off to production release);
    2) Product Engineering (support both NPI product development and production sustaining);
    3) Product management marketing (product definition, follow up with product development team for product spec assurance, product lifecycle management);
  • Skills:
    1) thorough understanding of IC development flow, capability of develop and maintain a project tracking sheet. Understanding of the development flow of a solution product is a plus;
    2) project manpower & expense control and other resource allocation;
    3) capability to drive team work to address internal and/or customer issue;
    4) willingness to learn new products/technologies.

Product Engineer (Senior)

产品工程师

Shanghai China

Responsibilities:

  • 熟练将新产品自工程阶段逐渐导入风险试产和量产阶段, 建立并实施对量产产品生产测试过程中的各种有效监控，及时发现异常并解决问题；
  • 熟练进行新产品的合格率评估，制定目标产品合格率；
  • 熟练进行产品失效分析，运用多种分析手段，结合理论原理，找到失效原因和对策，提升产品合格率。对低合格率的产品批次进行失效分析, 提出可行的解决方案；
  • 收集分析PCM/WAT 数据，结合FT测试数据，与晶圆厂合作一起优化工艺，提高晶圆良率;
  • 支持产品功能、性能、可靠性测试和评估工作;

Qualifications:

  • 电子工程、微电子或相关专业硕士;
  • 5年以上相关工作经验;
  • 熟练掌握产品失效分析技能、产品合格率评估技能;
  • 了解产品测试的基本原理与可靠性测试。

Production Planner

生产计划工程师

Shanghai China

Responsibilities:

  • Work with sales and PM to make production plan.
  • OSAT supplier’s management, release work order, follow up supplier’s production schedule to make sure on time delivery.
  • Work with internal relative teams to solve abnormal problems at supplier.
  • Be responsible for the statistics and summary of production data, and ensure the master production plan is updated in time.
  • Inventory management of semi-finished products.
  • Other assigned tasks.

Qualifications:

  • College education or above.
  • 2 years or above planning and purchasing or related working experiences.
  • Quick response on fluctuated and support to urgent demand.
  • Strong communication skills with internal and external teams.
  • Team player and can work under pressure.
  • Good data analysis capability.
  • ERP experience is a priority.

Recruiter

招聘专家

Shanghai China, Shenzhen China

Responsibilities:

  • Perform full life-cycle recruiting from initial contact, offering to safe on boarding.
  • Build a strong candidate pipeline through job boards, referrals, social networks, social media, etc.
  • Deliver highly qualified candidates in a fast-paced technical environment.
  • Proactively map organizations and markets to identify the best talents.
  • Act as brand ambassador to deliver an exceptional candidate experience throughout the recruiting life cycle.
  • Support campus recruiting program.
  • Edit and post recruiting advertisements in such channels as job boards, WeChat, H5 and social media.
  • Other tasks assigned by line manager.

Qualifications:

  • Bachelor Degree.
  • 3 years’ recruiting experience of technical positions in semiconductor industry with minimal 1-year focus on IC R&D positions.
  • Having some overseas or niche recruiting channels/ resources will be a plus.
  • Good influencing, negotiation and communication skills.
  • Good English in both written and oral.
  • Team work spirits and high efficiency.

Executive Admin

行政主管

Shanghai China

Responsibilities:

  • Work with management / executives on customer discussions and product marketing.
  • Work with management / executives on investor relations and public relations.
  • Contact person and project lead for R&D funding proposals, and project follow-ups.
  • Other assigned tasks, related to executing management team’s needs.

Qualifications:

  • College education or above.
  • 2 years or above on public relations, customer engagement, and product follow-ups.
  • Quick response on fluctuated and support to urgent demand.
  • Strong communication skills with internal and external teams.
  • Well-organized, detailed, and aware of time-scheduling pressures.
  • Team player and can work under pressure.
  • Good data analysis capability.
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