Revenue from Ethernet Switches (Dell Oro)
Ethernet port volumes (Dell-Oro)

Opportunity: Datacenter

The amount of data traversing the cloud-datacenter is increasing exponentially, requiring more ports and higher-speed/port.

There are several major drivers for this growth:

1) Increased work-from-home, requiring workers to do more in the cloud
2) AI workloads, increasing data sent to/and from memory to GPUs to process data

As a result, datacenters require incessant demands on datarates, increasing from 10G-25G-100G-200G-400G. While the newest systems require 400G, 800G, and 1.6T per port, the major number of transceiver volumes are still dominated by the lower-speed datarates from 1G-10G-25G-100G. Hence, there still exists significant demand for 'legacy' products, especially in enterprise and non-hyperscale cloud-computing applications.


PhotonIC Advantage: CMOS vs. SiGe

Competitors for optoelectronic chips used in datacenter optics utilize an exotic SiGe process (8-inch wafer). While this special SiGe process has the best analog performance (Gain-Bandwidth) versus standard-CMOS (12-inch wafer), it has several major limitations:
#1: Lowest-Cost
CMOS wafer (12-inch) provides nearly 2.5x more dies per wafer than a SiGe wafer (8-inch). Hence, based purely on wafer cost, the fundamental price/mm2 can be as much as 50% lower cost.
#2: Digital Integration
High-speed signaling requires higher speeds, less timing certainty, and therefore less signal-to-noise. On-chip digital processing is necessary at these higher speeds, in order to enable new digital-only features, such as: on-chip eye monitor, closed-loop digital calibration, nonlinear equalization, and FEC (forward error correction).
#3: Supply-Chain Risk Uncertainty
This specialized SiGe 8-inch fab typically is only found in small foundries based in North America. Whereas a CMOS 12-inch fab can be found in multiple locations worldwide, including Taiwan, Korea, China, Germany, and elsewhere. Hence, the supply chain is more diversified and prevents any one location from being a bottleneck.
#4: Pin-Compatible
PhotonIC chips are pin-to-pin compatible to competitors' previous offerings, enabling customers to do easy evaluation and testing. This pin-to-pin die geometry enables simpler supply-chain management and multiple sources for a particular product.
PhotonIC is unique from its competitors, in that for our high-volume NRZ products (40G, 25G, 100G), we utilize a standard CMOS to operate at 25Gbps datarates for optical communications. Several patents have been filed and published, key IP that enables CMOS process to achieve the performance as a SiGe performance -- at half the price.

NOTE: While CMOS is good for some products that require intensive analog/digital integration, it is not optimized for analog-intensive applications. Hence, PhotonIC uses SiGe process where necessary, as well as CMOS process -- depending on product lines. For example, our active-copper-cable (ACC) products below are mostly analog, so we utilize SiGe for those.
4x10G VCSEL Driver + TIAPHXT8104 & PHXR8104
CMOS2mm x 1.6mm (Pin-Compatible)Mass Production
1x25G VCSEL Driver + TIA
PHXT8201 & PHXR8201
CMOS1.5mm x 2mm (20% smaller vs competitor)Mass Production

4x25G VCSEL-Driver + TIA
PHXT8204 & PHXR8204
MMF: 100G-SR4
CMOS2mm x 3mm (Pin-Compatible), 1.8W (Module), -9dBm at HTSmall-Volume Production
4x25G DML-Driver + TIA
CMOSPendingUnder Development
1x50Gbps-PAM4 DML Driver + TIA
PHLD5601 & PHTA5601
5G Mid-haul, 50G DML
SiGeUnder Development
4x50Gbps-PAM4 DML Driver + TIA
PHLD5604 & PHTA5604
QSFP56 200G DR4/FR4
SiGeUnder Development
4x100Gbps-PAM4 DML Driver + TIASiGeUnder Development
50G/100G PAM-4 Retimer
QSFP56: 200G/400G DR4/FR4
CMOS & SiGeResearch
ACTIVE COPPER CABLESProductApplicationProcessStatus
2 x 28G-NRZ Limiting Redriver
25G & 100G (7m-distance)SiGeMass Production
2 x 56G-PAM4 Linear Redriver
PHRD6512200G & 400G (5m-distance)SiGeMass Production
4 x 100G-PAM4 Linear RedriverPHRD8512400G & 800G (3m-distance)SiGeUnder Development

28Gbps VCSEL at High-Temp: Mass Production

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